SILM Seminar

The SILM seminar features up to two presentations, one day per month from September 2019 to March 2020 on the security at the software/hardware interface. Following the format of its siblings, presentations will take place at INRIA, Rennes, France.

Practical information

The seminar is usually held one Friday per month between 10h and 12h at INRIA, on the Beaulieu campus in Rennes (France).

Seminars are open to the public. But to be allowed to enter the building, please register first by sending a mail with your names and affiliation to Nadia Derouault (nadia.derouault@inria.fr) and present an ID at the front desk.

Register to the mailing list at https://sympa.inria.fr/sympa/subscribe/silm-seminar to get info on the next talks.

Videoconference (live stream)

To join :

– connect to https://visio.inria.fr (<login>@inria.fr) and “Meet” : seminaire.silm@visio.inria.fr (PIN : 4875#)

– for external collaborators : https://visio.inria.fr/invited.sf?secret=O3A9s9dvp2Mvl4xKwR8yWw&id=305424998

– from a visioconference endpoint : call visio.inria.fr then enter the call ID : 305424998# (PIN : 4875#)

– phone: +33 4 92 38 77 88 (77788), then enter 305424998# (PIN : 4875#)

Contacts

Ronan Lashermes, INRIA, (+33|0)2 99 84 72 84, ronan.lashermes@inria.fr

Guillaume Hiet, CentraleSupélec, guillaume.hiet@centralesupelec.fr

Past presentations
November 8th, 2019

Lucas Davi (University of Duisburg-Essen) : Memory Corruption Attacks in the Context of Trusted Execution Environments

ARM TrustZone and Intel Software Guard Extensions (SGX) offer hardware-assisted trusted execution environments (TEEs) to enable strong isolation of security-critical code and data. They also allow systems to perform remote attestation, where a device challenges another device to report its current state. In this talk, we elaborate on remote attestation schemes that do not only attest static properties, but also cover run-time control-flow behavior of applications based on ARM TrustZone. While TEEs enable secure attestation of control-flow behavior, memory corruption attacks (e.g., return-oriented programming) inside TEEs can undermine remote attestation schemes. This talk will elaborate on memory corruption attacks for the use-case of SGX and how we can develop analysis approaches to detect vulnerable TEE code.

January 17th, 2020 (Pétri-Turing room / 10h-12h)

Billy Brumley (Tampere University of Technology) : Port Contention for Fun and Profit

Simultaneous Multithreading (SMT) architectures are attractive targets for attackers with side-channel expertise. SMT inherently offers a broader attack surface, exposing more microarchitecture components per physical core for fine-grain attacks. PortSmash (CVE-2018-5407) is a technique that abuses the execution units to exploit port contention, and creates a high-resolution timing side-channel capable of leaking confidential information. PortSmash affects both Intel and AMD architectures featuring SMT technology and due to its nature, it is capable of targetting shared libraries, static builds and even SGX enclaves.

Yann Loisel (SiFive, RISC-V) :  Embedded security around RISC-V cores

The security needs increase a lot in our connected world. Beyond the perception the software can satisfy the security requirements, it’s obvious that the best solutions could only be a combination of hardware and software mechanisms.
The huge activity around the RISC-V cores these last years is not only a buzz or for an unjustified reason. On the contrary, this ecosystem is more than only a new ISA: it is the ideal playground for applying the best practices in embedded security.
We will see in this talk what the RISC-V foundation and its academic and industrial members propose for making RISC-V a synonym of security at the core, in the software and at the system level.

Upcoming presentations
February 18th, 2020 (Pétri-Turing room)

Lee Smith (Arm fellow), Frédéric Piry (Arm fellow), Arnaud de Grandmaison ( senior principal engineer ) : Fruitful security (and more) from CHERI to Morello

Security is the greatest challenge computing needs to address to meet its full potential. Memory safety issues have been for far too long and way too common in the field, with the first partially documented one dating from 1972 ! Almost 50 years later, it’s obvious the situation has only gotten worse, with for example Microsoft (and this is not specific to them) recognizing that 70% of all security bugs in their products are memory safety issues.

Capability-based (software managed but hardware enforced tokens of authority used to access memory) systems have been researched and used since the very beginning of computing, but they have been set aside by segmentation/pagination-based systems for price, performance and ease of implementation reasons. Arm has been working with the University of Cambridge for several years to come up with Morello, an Arm implementation of the CHERI architecture, to address security with strong fundamental principles. This is a big and critical project, as recognized by the large funding from the UK government (£70 million), and the £117 million additional contribution from the “Digital Security by Design” partners.

This presentation will first introduce capability-based systems in general, and CHERI specifically then focus on Morello. Transitioning to capabilities is challenging and disruptive enough, at all levels from the hardware up to the software, system, debug, … that this is the right time to look at those (not so) new systems again, hopefully benefiting from 50+ years of experience, if not errors, in security. This is effectively a call to arms (pun intended !) for a joint research – industry collaboration effort.

March 20th, 2020

Frank Piessens (KU Leuven): TBD

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